CSE 260

Digital Computers I:
Organization and Logical Design
Fall 2007
 

Course description (from the catalog)

Digital computers and digital information processing systems; Boolean algebra, principles and methodology of logic design; machine language programming; register transfer logic; microprocessor hardware, software and interfacing; fundamentals of circuits and systems; computer organization and control; memory systems, arithmetic unit design. Occasional laboratory exercises. Prerequisites: CSE 131 or 126. Credit: 3 units.

Additional Information

This is a first course in digital logic design and elements of computer architecture. The course covers much of the Wakerly textbook. The book comes with a CD ROM for the student edition of the Xilinx logic design tools. These will be used throughout the course, in both lectures and homework. Schematic capture, VHDL and logic simulation will all be introduced and used fairly extensively. The tools are also available from the Xilinx web site (details below).

Administrivia

• Time: Monday, Wednesday 1:00-2:30
• Place: Lopata Hall, 101.
• Text: Digital Design, Principles & Practices, 4e by John F. Wakerly; Lecture Notes for CSE 260  (available, September, in the bookstore)
• Professor David M. Zar, Bryan 307C, 935-4876, dzar@wustl.edu, 
• Office Hours: Tuesdays, 1:00-2:00 p.m. and Thursdays, 10:00-11:00 a.m. or by appointment (send me email or call me to schedule).
• Teaching Assistants: Eitan Marder-Eppstein (em4 AT cec), Ben Siepser (bns1 AT cec.wustl.edu)
• Grading: Class Participation: 10%, Quizzes: 15%, Design Problems: 25%, Mid Term: 25%, Final: 25%.
• Midterm Exam: October 10, 2007
• Final Exam: Thursday December 20, 1:00 PM - 3:00 PM .
• There will be no quiz/questions on September 12.

Class Preparation There are assignments for each class that will be posted on the web site (see table below). These include reading and doing a couple problems covered by the reading. Each class will start with a quick review of the material for that day. This is not intended as an in-depth review, but rather a chance for you to bring up questions that you could not work out before class. I will then pose questions for each of several students. Your responses to these questions will constitute your class participation grade. (Note that if you are one of the people I call on but you're not there, you will get zero credit for that question. If you plan to be absent, be sure to let me know in advance. Email is fine.) We'll typically spend the remainder of the class on some activity/lecture that will give you a chance to further deepen your understanding of the material and develop your design skills.

Problem Sets and Quizzes. Quizzes will be given weekly, every Wednesday when problem sets are due. Quiz problems are based directly on problem sets. The problem sets will appear on the web site. The web site provides both the problems and the solutions. You are strongly encouraged to work the problems on your own before consulting the solutions. This is the best preparation for the quizzes. Problem sets are not collected or graded. However, the course TAs will review your solutions on request and will help you with any questions you may have. You are encouraged to form study groups and to work with your fellow students to improve your understanding of the course material, but don't let this become a crutch. The only way to really learn the material is to work problems on your own.

On quizzes and exams you will not be allowed to use any calculation device. Please know how to do arithmetic and base conversions without such aids.  The two exams are closed-book except that you will be allowed one 8.5x11 inch cheat-sheet that will be handwritten (no photocopies or mechanical productions).  Quizzes are strictly closed-book with no cheat-sheet allowed.

Design Problems. The design problems involve use of computer-aided design tools to design and simulate circuits to solve particular problems. Several design problems will be assigned during the semester. Some of these require considerable time and effort. Do not leave them to the last minute. You are expected to do ALL your own work on design problems. You may discuss general approaches to the design problems with your fellow students, and the TAs will provide hints and general guidance to point you in the right direction. However, you are expected to turn in your own work and only your own work. You should not share any specific details of your design with other students. Sharing of schematics, VHDL code, simulation output or any other written material is expressly forbidden. Any group of students found to have collaborated inappropriately on a design problem will have the full value of the design problem deducted from the grades of all students involved. Repeat offenses will not be treated so leniently.

Expectations. This course covers a great deal of material and you will need to devote substantial time and effort to mastering it. You should plan to read the textbook, work problem sets and do the design problems. You cannot expect to learn the material simply by attending class. Engineering is not a spectator sport. It requires your active and energetic participation. The good news is that the more you let yourself get involved in what you're doing, the more you will learn and the more you will enjoy the creative and inventive aspects of engineering that make it both fun and rewarding.

Late Policy. Design problems are due at the beginning of class on the day indicated. Solutions will be posted on the web site after the due date. Late submissions will not be accepted, not even for partial credit. No exceptions. If, for some reason, you cannot make it to class, have a friend bring it or turn it in to the instructor any time before the class when due. If you come late to a class or have to leave early and miss a quiz or are called on for a question, you will receive no credit unless prior arrangements have been made.

On-line Communication. Most information about the course can be obtained electronically. All homework will be posted online as well as the solutions.

There is also a link to the web site for the textbook. This includes supplementary material that I encourage you to peruse and answers to selected textbook problems. In addition, the course web site has a link to the Xilinx web site, which you will find useful when we start to use the Xilinx CAD software.

Computer Aided Design Tools. The course makes extensive use of the Xilinx design tools. I STRONGLY RECOMMEND that you install the tools on a personal PC if you have access to one, since CEC can get busy and at times the software might not be available. They will run fine on a laptop (I do it all the time). They require close to 2 GB of disk space for installation and in general, the more memory you have the better (512 MB is adequate). They run fine on a 1 GHz class machine.

The tools are also available in the Urbauer labs (115/116) and login information will be posted in class.

Consulting Hours. The primary role of the TAs in this course is to help you learn the material. All of the TAs hold regular consulting sessions. (Times below.) If you're having trouble with the problem sets, or need some guidance to help you get started on a design problem, take the time to go see the TAs, and they will do their best to help you. Don't expect them to do your work for you. They are there to help you learn how to do it yourself.  Unless otherwise noted, all will be in the Urbauer labs (Urbauer 115/116).

	11:00 a.m.-1:00 p.m.	11:30-1:30 p.m.	2:30-4:30 p.m.
Saturday
Sunday		Ben
Monday			Eitan
Tuesday			Ben
Wednesday	Eitan

Examinations. There will be two exams given during the semester, during class periods. The mid-term exam is scheduled for Wednesday, October 10, in class. If this date needs to change, it will be announced at least two weeks prior to the exam date. The final exam will be given on Thursday December 22, 1:00 PM - 3:00 PM (not subject to change).

Before Class Assignments

Course Outline

1. Digital Computers and Information -- 2 lectures
   • Elements of computer architecture
   • Programming a simple computer
   • Number systems
   • Arithmetic operations
   • Information coding
2. Introduction to Digital Logic -- 5 lectures
   • Binary logic and gates
   • Boolean algebra
   • Schematic capture and logic simulation
   • Standard forms
   • Logic simplification using Karnaugh maps
   • NAND, NOR gates
   • EXOR gates and parity generation
   • Integrated circuits
3. Combinational Logic Design -- 3 lectures
   • Hierarchical design
   • Analysis of comginational circuits
   • Design procedures
   • Encoders and decoders
   • Multiplexors and demultiplexers
   • Binary arithmetic circuits
   • Representing negative numbers
   • Introduction to VHDL
4. Sequential Circuits -- 5 lectures
   • Latches and flip flops
   • Sequential circuit analysis
   • Designing sequential circuits
   • Designing sequential circuits with VHDL
5. Registers, Counters and Complex Sequential Circuits -- 3 lectures
   • Registers with serial and parallel IO
   • Serial addition
   • Basic synchrononous counters
   • Counters with carry lookahead
   • Designing non-standard counters
   • Traffic Light controller
6. Design of a Simple Computer -- 3 lectures
   • Fetch and execute cycle
   • Processor organization
   • Data transfer using buses
   • Registers and ALU design
   • Control and sequencing
7. Memory and Processor Performance -- 3 lectures
   • Random access memory
   • Tristate buffers
   • Static RAM organization
   • Reading and writing static RAMs
   • Building larger memory arrays
   • Dynamic RAM
   • Memory latency and its impact on performance
   • Using multiple registers
   • Caches
   • Pipelining
8. Programmable Logic Devices -- 1 lecture
   • Read-only memory
   • PLAs and PALs
   • Field programmable gate arrays

Prepared by David M. Zar: dzar@wustl.edu, Updated Monday, October 22, 2007 .