Introduction to design methods for digital logic and fundamentals of computer architecture. Boolean algebra and logic minimization techniques; sources of delay in combinational circuits and effect on circuit performance; survey of common combinational circuit components; sequential circuit design and analysis; timing analysis of sequential circuits; use of computer-aided design tools for digital logic design (schematic capture, hardware description languages, simulation); design of simple processors and memory subsystems; program execution in simple processors; basic techniques for enhancing processor performance; configurable logic devices. Prerequisites: CSE131/CS101G or 126/136G or comparable programming experience.
This is a first course in digital logic design and elements of computer architecture. The course covers much of the Wakerly textbook. The book comes with a CD ROM for the student edition of the Xilinx logic design tools. These will be used throughout the course, in both lectures and homework. Schematic capture, VHDL and logic simulation will all be introduced. Additional information on installing and using the tools will be given in class and via the class notes.
Problem Sets and Quizzes. Quizzes will be given weekly, every Wednesday
when problem sets are due.
Quiz problems are based directly on problem sets. The problem sets will appear
on the
web site. The web site provides both the problems and the solutions.
You are strongly encouraged to work the problems on your own
before consulting the solutions. This is the best preparation for the quizzes. Problem sets are not collected or graded. However, the course
TAs will review your solutions on request and will help you with any
questions you may have. You are encouraged to form study groups and to
work with your fellow students to improve your understanding of the
course material, but don't let this become a crutch. The only way
to really learn the material is to work problems on your own.
On quizzes and exams, you will not be allowed to use any calculation device.
Please know how to do arithmetic and base conversions without such aids.
The quizzes and the two exams are closed-book/closed notes (no cheat-sheets
allowed).
Design Problems. The design problems involve use of computer-aided design tools to design and simulate circuits to solve particular problems. Several design problems will be assigned during the semester. Some of these require considerable time and effort. Do not leave them to the last minute. You are expected to do ALL your own work on design problems. You may discuss general approaches to the design problems with your fellow students, and the TAs will provide hints and general guidance to point you in the right direction. However, you are expected to turn in your own work and only your own work. You should not share any specific details of your design with other students. Sharing of schematics, VHDL code, simulation output, or any other written material is expressly forbidden. Any group of students found to have collaborated inappropriately on a design problem will have the full value of the design problem deducted from the grades of all students involved. Repeat offenses will not be treated so leniently.
Expectations. This course covers a great deal of material, and you will need to devote substantial time and effort to mastering it. You should plan to read the textbook, work problem sets, and do the design problems. You cannot expect to learn the material simply by attending class. Engineering is not a spectator sport. It requires your active and energetic participation. The good news is that the more you let yourself get involved in what you're doing, the more you will learn and the more you will enjoy the creative and inventive aspects of engineering that make it both fun and rewarding.
Late Policy. Design problems are due at the beginning of class on the day indicated. Solutions will be posted on the web site after the due date. Late submissions will not be accepted, not even for partial credit. No exceptions. If, for some reason, you cannot make it to class, have a friend bring it or turn it in to the instructor any time before the class when due.
On-line Communication. Most information about the course can be obtained electronically. All homework will be posted online as well as the solutions.
There is also a link to the web site for the textbook. This includes supplementary material that I encourage you to peruse and answers to selected textbook problems. In addition, the course web site has a link to the Xilinx web site, which you will find useful when we start to use the Xilinx CAD software.
Computer Aided Design Tools.
The course makes extensive use of the Xilinx student edition design
tools (or, alternatively, the free
Xilinx WebPACK
design tools). These are a slightly scaled-down version of a standard
commercial CAD package.
I STRONGLY RECOMMEND that you install the tools on a personal
PC if you have access to one, since CEC can get busy and at times the software
might not be available.
The tools run under Windows XP without any trouble.
They will run fine on a laptop.
They require close to 1.1 GB of disk space for installation,
and, in general, the more memory you have the better
(128 MB is adequate). They run fine on a 300 MHz class machine.
The tools are also available in the Urbauer labs (115/116), and login information
will be posted in class.
Consulting Hours. The primary role of the TAs in this course
is to help you learn the material. All of the TAs hold regular
consulting sessions. (Times below.) If you're having trouble
with the problem sets, or need some guidance to help you get started
on a design problem, take the time to go see the TAs, and they
will do their best to help you. Don't expect them to do your work for
you. They are there to help you learn how to do it yourself. Unless
otherwise noted, all office hours will be held in the Grader's Office (Urbauer 114).
| 10:00 a.m.- noon. | 11:00 a.m. - 1:00 p.m. |
11:45 - 1:45 p.m. | 2:00 - 4:00 p.m. | 4:00 - 6:00 p.m. | |
| Saturday | Eitan | ||||
| Sunday | Ben | ||||
| Monday | Eitan | ||||
| Tuesday | Marty | Ben | |||
| Wednesday | Marty |
Examinations. There will be two exams given during the semester during class periods. The mid-term exam is scheduled for Wednesday, October 18, in class. If this date needs to change, it will be announced at least two weeks prior to the exam date. The final exam will be given on Monday December 11, 1-2:30 p.m. The Dean can resolve any final exam conflicts that you identify now (at the beginning of the semester) and report to the Dean's office. It is your responsibility to check for final exam schedule and report all conflicts. Since all conflicts can be resolved if you simply report them, you will not be allowed to schedule a special exam time for this course to resolve a conflict you identify at the end of the semester. You will be required to convince the instructor of the course with the conflicting exam time to schedule a special exam time for that course. No exceptions will be made to this policy, so you really need to check your final exam schedule at the beginning of the semester.
Prepared by William D. Richard, Ph.D., wdr@wustl.edu, Updated Wednesday, November 29, 2006 .