library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity loopVHDL is
   Port (  A:   in std_logic_vector(7 downto 0) ;
           B:   in std_logic_vector(7 downto 0) ;
           S:   out std_logic_vector(7 downto 0)) ;
end loopVHDL ;

architecture Behavioral of loopVHDL is
begin
   process(A,B)
   begin
      for i in 0 to 7 loop
         S(i) <= A(i) AND B(i) ;
      end loop ;
   end process ;
end Behavioral ;