library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HalfAdderVHDL is
   Port (Ci : in std_logic ;
           A:   in std_logic ;
           S:   out std_logic ;
           Co: out std_logic) ;
end HalfAdderVHDL ;

architecture Behavioral of HalfAdderVHDL is
begin
   S <= Ci xor A ;
   Co <= Ci and A ;
end Behavioral ;