Simulating the 260 CPU

The CPU VHDL code that has been supplied as well as the do file, comprise everything you need to run your first CPU simulation. You should not use the Xilinx front-end, however, if you want to make your life easier (and if you want to use the do file). If you do use the Xilinx tools, you'll need to create a testbench with reset and clock and manually add signals to your output. Using the supplied files, however, you can get things running much quicker.

What you will do is use the ModelSim simulator by itself. This simulator has its own project environment and will allow you to create projects, put files in them, compile the files and run simulations. In fact, it's quite easy to do and that's what is described below.

  1. Copy the VHDL code from the web site to a file on your computer (I'll refer to this as cpu.vhd).
  2. Copy the do file to you computer (I'll call this cpu.do)
  3. Run ModelSim stand-alone (you can find MXE, as Xilinx calls it, in C:\Modeltech_xe assuming you installed it in the default location). You should have a shortcut to this in your Start->Modelsim menu or on your desktop. If you can't find it, check for C:\Modeltech_xe\win32xoem\modelsim.exe (again, assuming you installed in the default location). Also, ignore any warnings about this being a starter license and such. Once you run this, you should see a window like:



    This is the same window you've seen, before, when running from within the Xilinx tools, but nothing will be run for you at this point.
  4. To create a new project for your CPU design, select File->New->Project from the menu. Enter a name for the project and check the directory where this project will be created. By default, it uses an examples directory but you can change this to any location you choose (and I suggest you create a new directory for the CPU project). Leave the Default Library Name as work.
  5. Once you create a new project you will be able to add files to it (much the same way you do in the Xilinx tools). Use Project->Add File to Project... and select your cpu.vhd file from where ever you saved it. You will have the choice of copying it or referencing it from the current location. I suggest you copy it so that you will have the original if you have problems, later.
  6. Once the file is added, you can also add the cpu.do file into your project. While not required, this will make your life a bit easier later on.
  7. At this point, things should look similar to this:


     

  8. You see your two source files and note the asterisk (*) by the VHDL file. This means the file is out-of-date and needs to be compiled. You cannot run a simulation until you compile the VHDL code. Before you compile, however, you need to set up the configuration for the compiler.

    NOTE: This screenshot is for version 5.x of Modelsim. Version 6.x is slightly different. It will have a question mark (?) instead of the asterisk in a status column for out-of-date source files. Also, the following dialog box is slightly different, but you should still find a line to check for VHDL-1993 syntax.

    Right-click on the cpu.vhd file and select Properties... from the menu. Click on the VHDL tab and select Use 1993 Language Syntax and Use explicit declarations only.  The dialog should look like this:



    Click OK to accept these changes.
     

  9. Again, right-click on cpu.vhd and select Compile  to compile your design. You should have no errors or warnings. If you have any errors, check the above compiler settings. If they look right, close the project and re-open it and see if that works. Sometimes that will kick the compiler in the head, but usually the above works just fine. If you do not get the above settings right, it will not compile!

  10. Once your code is compiled, you can simulate (finally!). To do this, you have to tell the simulator what you want to simulate. You do this by clicking on the Library tab at the bottom of the left pane (where your code is listed). You will see the package as well as the entities that were in the source file.

  11. Double-click on top since this is the entity you wish to simulate. When you do, it loads that model and you should see a bunch of messages in the window. You should also see a new tab called sim appear and that's where you will be left. Now you can run the simulation.

  12. Assuming you copied cpu.do into your project, simply type "do cpu.do" and the simulation will begin; the wave window will open, all the necessary signals will appear and a simulation will run for 500 ns. You can zoom all to see it.

  13. To run the simulation for more time, type "run 1000" and it will run for 1000 ns, and so on. You can see the program in RAM run by doing this.

You're done! Everything else works just like it did using the Xilinx tool to setup the simulator. It's the same simulator! You can create cursors, zoom in/out, print, etc. If you want to view/edit your source code, go back to the Project tab and double-click on your VHDL file. If you make changes to your source, save it and note that the asterisk (*) will appear by your source file. Recompile it, select Run->Restart... and then uncheck every box before restarting the simulator. Type "do cpu.do" again and watch the simulation. (Optionally, right click on cpu.do in the Project tab and select execute to run the dofile.)