library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led is
    Port ( swt : in std_logic_vector(7 downto 0);
           led : out std_logic_vector(7 downto 0);
			  ssg : out std_logic_vector(7 downto 0);
			  an  : out std_logic_vector(3 downto 0));
end led;

architecture Behavioral of led is

begin
	led <= swt;
   an <= b"1111";
end Behavioral;